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Data Sheet No. PD94249
IRU3013
VRM 8.5 COMPATIBLE 5-BIT PROGRAMMABLE SYNCHRONOUS BUCK CONTROLLER IC WITH TRIPLE LDO CONTROLLER DESCRIPTION
The IRU3013 controller IC is specifically designed for Intel Pentium III microprocessor applications as described in the VRM 8.5 specification. The IC provides a single chip solution for the Vcore, 1.2V AGTL+, 1.8V and a third uncommitted LDO controller that can be used either as 1.2V power good detector or to provide 1.5V AGP bus in applications that this voltage is required. The IRU3013 features a patented topology that, in combination with a few external components, (*Note: See application current in figure 3) will provide in excess of 30A of output current for an onboard Vcore synchronous converter while automatically providing the output voltage specified in VRM 8.5 specification. The IRU3013 also features, loss-less current sensing by using the RDS(ON) of the high side Power MOSFET as the sensing resistor, a Power Good window comparator that switches its open collector output low when the output is outside of a 10% window. Other features of the device are: Under-voltage lockout for both 5V and 12V supplies, an external programmable softstart function, and the ability to program the oscillator frequency by connecting an external capacitor.
FEATURES
Meets Latest VRM 8.5 Specification Provides Single Chip Solution for Vcore, 1.2V AGTL+, 1.8V and VDDQ On-Board 5-Bit DAC and Decoder programs the output voltage from 1.050V to 1.825V Loss-less Short Circuit Protection Synchronous operation allows maximum efficiency Patented architecture allows fixed frequency operation as well as 100% duty cycle when operating with a changing load Minimum Part Count, No External Compensation Soft-Start High current totem pole driver for directly driving an external Power MOSFET Power Good Function
APPLICATIONS
Pentium III with VRM 8.5 Specification DC to DC Converters
TYPICAL APPLICATION
3.3V LINEAR CONTROL
VRM 8.5 VID
5V
VOUT2
SWITCHER CONTROL
VOUT1
IRU3013
LINEAR CONTROL LINEAR CONTROL
VOUT3
VOUT4
Figure 1 - Typical application of IRU3013.
Note: Pentium III is trade mark of Intel Corp.
PACKAGE ORDER INFORMATION
TA (C) 0 To 70 0 To 70
Rev. 1.2 09/06/01
DEVICE IRU3013CW IRU3013CQ
PACKAGE 24-Pin Plastic SOIC WB 24-Pin Plastic QSOP
1
IRU3013
ABSOLUTE MAXIMUM RATINGS
V5 Supply Voltage .................................................... 10V V12 Supply Voltage .................................................. 20V All Other Pins .......................................................... 7V Storage Temperature Range ...................................... -65C To 150C Operating Junction Temperature Range ..................... 0C To 125C
PACKAGE INFORMATION
24-PIN WIDE BODY PLASTIC SOIC (W)
TOP VIEW Ct 1 Lin1 2 VFB1 3 VFB2 4 V5 5 OVP 6 PGd 7 CS- 8 CS+ 9 HDrv 10 PGnd 11 Gnd 12 24 Lin2 23 D0 22 D1 21 D2 20 D3 19 D25 18 VFB3 17 SS 16 Lin4 15 VFB4 14 V12 13 LDrv Ct 1 Lin1 2 VFB1 3 VFB2 4 V5 5 OVP 6 PGd 7 CS- 8 CS+ 9 HDrv 10 PGnd 11 Gnd 12
24-PIN PLASTIC QSOP (Q)
TOP VIEW 24 Lin2 23 D0 22 D1 21 D2 20 D3 19 D25 18 VFB3 17 SS 16 Lin4 15 VFB4 14 V12 13 LDrv
JA =80C/W
JA =88C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over V12=12V, V5=5V and TA=0 to 70C. Typical values refer to TA=25C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature. PARAMETER VID Section DAC Output Voltage (Note 1) DAC Output Line Regulation DAC Output Temp Variation VID Input LO VID Input HI VID Input Internal Pull-up Resistor to 5V Power Good Section Under-Voltage Lower Trip Point Under-Voltage Upper Trip Point UV Hysteresis Over-Voltage Upper Trip Point Over-Voltage Lower Trip Point OV Hysterises Power Good Output LO Power Good Output HI Soft-Start Section Soft-Start Current SYM TEST CONDITION MIN 0.98Vs 4.5Rev. 1.2 09/06/01
2
IRU3013
PARAMETER UVLO Section UVLO Threshold - 12V UVLO Hysteresis - 12V UVLO Threshold - 5V UVLO Hysteresis - 5V Error Comparator Section Input Offset Voltage Delay to Output Current Limit Section CS Threshold Set Current CS Comp Offset Voltage Hiccup Duty Cycle Supply Current Section Operating Supply Current Output Drivers Section Rise Time Fall Time Dead Band Time Oscillator Section Osc Frequency Osc Valley Osc Peak LDO Controller Section VFB1 and VFB2 (Pins 3 and 4) VFB4 (Pin 15) Input Bias Current Lin 1, 2, 3 Drive Current OVP Section OVP Threshold OVP Source Current D25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 SYM TEST CONDITION Supply Ramping Up Supply Ramping Up -2 VDIFF = 10mV 120 -5 Css = 0.1F CL = 3000pF V5 V12 CL = 3000pF CL = 3000pF CL = 3000pF Ct = 150pF 20 14 70 70 200 220 0.2 V5 1.200 0.800 2 30 1.17Vs 5 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Vs 1.300 1.350 1.400 1.450 1.500 1.550 1.600 1.650 1.700 1.750 1.800 1.050 1.100 1.150 2.200 2.250 D25 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 100 130 150 MIN TYP 9 0.5 4 0.3 +2 100 200 +5 2 MAX UNITS V V V V mV ns A mV %
mA ns ns ns KHz V V V A mA V mA Vs 1.325 1.375 1.425 1.475 1.525 1.575 1.625 1.675 1.725 1.775 1.825 1.075 1.125 1.175 1.225 1.275
Note: Vs refers to the set point voltage given in table 1.
Table 1 - Set point voltage vs. VID codes.
Rev. 1.2 09/06/01
3
IRU3013
PIN DESCRIPTIONS
PIN# 1 2 3 4 5 6 7 8 9 PIN SYMBOL Ct Lin1 VFB1 VFB2 V5 OVP PGd CSCS+ PIN DESCRIPTION This pin programs the oscillator frequency in the range of 50 KHz to 500KHz by means of an external capacitor connected from this pin to the ground. Controls the gate of an external MOSFET for the AGTL+ linear regulator or 1.8V supply. This pin provides the feedback for the linear regulator that its output drive is Lin1 pin. This pin provides the feedback for the linear regulator that its output drive is Lin2 pin. 5V supply voltage. This pin provides an over voltage flag when the feedback pin VFB3 voltage exceeds 17%(Typical) of the set point for the Vcore output. This pin is an open collector output that switches LO when the output of the converter is not within 10% (typ) of the nominal output voltage. When PGd pin switches LO the output saturation voltage is less than 0.4V at 3mA. This pin is connected to the Source of the power MOSFET for the Core supply and it is the negative input for the internal current sensing circuitry. This pin is connected to the Drain of the power MOSFET of the Core supply. It provides the positive sensing input for the internal current sensing circuitry. An external resistor programs the CS threshold depending on the RDS of the power MOSFET. An external capacitor is placed in parallel with the programming resistor to provide high frequency noise filtering. Output driver for the high side power MOSFET. This is the power ground pin and must be connected directly to the gnd plane close to the source of the synchronous MOSFET. A high frequency capacitor (typically 1F) must be connected from V12 pin to this pin for noise free operation. This pin must be connected directly to the ground plane. A high frequency capacitor (0.1 to 1F) must be connected from V5 and V12 pins to this pin for noise free operation. Output driver for the power MOSFET, which is used as a synchronous switched rectifier. This pin is connected to the 12V supply and serves as the power Vcc pin for the output drivers. A high frequency capacitor (0.1 to 1F) must be connected directly from this pin to Gnd pin in order to supply large instantaneous current pulses to the power MOSFET during the transitions. This pin provides the feedback for the linear regulator that its output drive is Lin4 pin. This pin controls the gate of an external MOSFET for either the AGP Bus linear regulator or can be used as Power good detector for 1.2V AGTL+ bus. This pin provides the soft-start for the switching regulator. An internal current source charges an external capacitor that is connected from this pin to the ground which ramps up the outputs of the switching regulator, preventing the outputs from overshooting as well as limiting the inrush current. The second function of the Soft-Start cap is to provide long off time (HICCUP) for the synchronous MOSFET during current limiting. This pin is connected directly to the output of the Core supply to provide feedback to the Error comparator. This pin programs the output voltage in 25mV steps based on the VID table. 40K internal pull-up to Vcc. MSB input to the DAC that programs the output voltage. This pin can be pulled-up externally by a 10K resistor to either 3.3V or 5V supply. 40K internal pull-up to Vcc. Input to the DAC that programs the output voltage. This pin can be pulled-up externally by a 10K resistor to either 3.3V or 5V supply. 40K internal pull-up to Vcc. Input to the DAC that programs the output voltage. This pin can be pulled-up externally by a 10K resistor to either 3.3V or 5V supply. 40K internal pull-up to Vcc. LSB input to the DAC that programs the output voltage. This pin can be pulled-up externally by a 10K resistor to either 3.3V or 5V supply. 40K internal pull-up to Vcc. Controls the gate of an external MOSFET for the AGTL+ linear regulator or 1.8V supply.
10 11 12 13 14
HDrv PGnd Gnd LDrv V12
15 16 17
VFB4 Lin4 SS
18 19 20 21 22 23 24
VFB3 D25 D3 D2 D1 D0 Lin2
4
Rev. 1.2 09/06/01
IRU3013
BLOCK DIAGRAM
18 Enable V12 Vset Enable 10
VFB3 HDrv PGnd LDrv CSCS+
V12 V5
14 5
UVLO
Vset
+ Slope Comp Soft Start & Fault Logic
PWM Control Osc
11 V12 13
D0 D1 D2 D3 D25 VFB1 Lin1
23 22 21 20 19
Enable
5Bit DAC, Ctrl Logic
8 Over Current 9
200uA
Enable 1
3 17 2 1.17Vset 6
Ct SS
OVP
Lin2 VFB2
1.2V 24 4 1.1Vset 7 0.8V 16 15 12
PGd Gnd
Lin4 VFB4
0.9Vset
Figure 2 - Simplified block diagram of the IRU3013.
Rev. 1.2 09/06/01
5
6
L1 Sanyo: 10MV1500DX/GX 1.2uH C3A1 1500uF 10V C3B1 1500uF 10V IRF3704S TO263 Q3 close to pin 18 R5 1K5 C10A1 C10B1 C10C1 C10D1 C10E1 C10F2 C10F1 1500uF 1500uF 1500uF 1500uF 1500uF 1500uF 1500uF 10V 10V 10V 10V 10V 10V 10V C6 1uF close to pin 5 R4 5.1 0805 R8 10K R9 47K 1% close to pin 18 IRF3704S close to pin 18 TO263 R6 2.2 R7 100 1% close to pin 18 0805 R3 3.3K Q1 IRF3711 TO-263 Q2 D1 30BQ015 SMC size R1 10 0805 C3 470pF R2 3K3 close to pin 18 C4 1uF VCORE @ 30A peak C3B2 1500uF 10V C2 220PF 2.2uH 5052 core with 5 turns Sanyo: 10MV1500DX/GX of 1.2mm wire L2 6018 core with 7 turns of triple 0.7mm wire C1 1000uF 6.3V C5 1uF close to pin 14 R10 10 Vcc Type Detect#
IRU3013
+5VIN
12V
PWM_En
14 9 12 2
close to gate R12 100, 1% R13 10K, 1% close to pin 3 R14 432, 1% Q6 2N7002 R15 100, 1% VID4 VID3 VID2 (VID25) R17 100
Vcc Enable Vcore PWM
C19 1uF Q10 2N7002 TUAL5
5 10
PMBT2222A close to pin 3 R11 100
8 13 11
18
Q4
TYPICAL APPLICATION
C9 0.22uF
17
IRU3013
1 3 19 20 21 22 24 4 23 6 16 15 7
close to pin 3
C8 180pF close to pin 1 R18 47K TUAL5# VID1 VID0 R16 close to pin 4 10K, 1% close to pin 4 close to gate pin C12 1nF close to gate pin C14 220uF R19 10K
C7 1nF close to gate
Q5 Vcc3(ATX) IRLR3103 TO252 VDDQ (1.5V/3.3V @ 2A avg) C10 1500uF/6.3V TUAL5#
Q8 2N3904
Q7 IRLR024 TO252
C13 1000uF 6.3V
Vtt(1.2V/1.5V) C11 1000uF 6.3V VRM_Power Good C15 0.1uF
R23 10K R24 47K D2 1N4148 Q11 2N3904 R26 680 510 R27 1K R25
R20 12.6K, 1%_Intel, SIS 21.3K, 1%_VIA close to pin 15 R21 10K, 1% close to pin 15 R22 100 close to gate pin
Vtt_PGood
Vcc3(ATX)
Vtt(1.25/1.5)
C16 1nF close to gate pin
Q9 IRLR024 C18 TO252 220uF
C17 1500uF/10V
Vcc 1.8V @ 2.5A peak_Intel, SIS Vcc 2.5V @ 2.5A peak_VIA
Vcc
C20 1uF Q12 2N7002 Clk_Gen_EN# R30 10K R32 2.2K VCC3
Vcc
VIA_CLK_GEN
R33
Vtt(1.25/1.5)
22K
R28 10K
Vcc12 Vcc3
R34 10K Q16 IRLML2803 Q15 2N3904
R29 1K TUAL5
Tualatin CPU
CPU, AF36 pin
R31 1K Q13 2N3904 SOT-23 Q14 2N7002 SOT-23
Figure 3 - Typical application of IRU3013 for VRM 8.5 specification.
Intel/SIS_CLK_GEN
VCC3_Clk_Gen_PWR
Q17 2N7002
TUAL5# Intel Reference Circuit - Auto CPU Select/Control
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 02/01
Power Sequence for Vtt and Vcore, Similar to that of Intel's
Rev. 1.2 09/06/01

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